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september 2010 dsc-5279/05 1 features 128k x 36, 256k x 18 memory configurations supports high system speed: commercial: C 150mhz 3.8ns clock access time lbo input selects interleaved or linear burst mode self-timed write cycle with global write control ( l ( gw), byte write enable ( bwe ), and byte writes ( bw x) 3.3v core power supply power down controlled by zz input 3.3v i/o optional - boundary scan jtag interface (ieee 1149.1 compliant) packaged in a jedec standard 100-pin plastic thin quad flatpack (tqfp). description theas8c403600/1800 are high- speed srams organized as 128k x 36/256k x 18. the as8c403600/401800 srams contain write, data, address and control registers. internal logic allows the sram to generate a self-timed write based upon a decision which can be left until the end of the write cycle. the burst mode feature offers the highest level of performance to the system designer,as the as8c403600/1800 can provide four cycles of data for a single address presented to the sram. an internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. the first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. if burst mode operation is selected (( adv =low), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. the order of these three addresses are defined by the internal burst counter and the lbo input pin. the as8c403600/1800 srams utilize the latest high- performance cmos process and are packaged in a jedec standard 14mm x 20mm 100-pin thin plastic quad flatpack (tqfp). pin description summary note: 1. bw 3 and bw 4 are not applicable for the AS8C401800. a 0 -a 17 address in puts input synchronous ce chip enab le input synchronous cs 0 , cs 1 chip se lects input synchronous oe output e nable input asynchronous gw global write enable input synchronous bwe byte write enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 (1) individual by te write se lects input synchronous clk clock input n/a adv burst ad dress advance input synchronous adsc address status (cache controller) input synchronous adsp address s tatus (processor) input synchronous lbo linear / interleaved b urst order input dc tms test mode select input synchronous tdi test d ata input input synchronous tck test clock input n/a tdo test d ata output output synchronous zz sleep mode input asynchronous i/o 0 -i/o 31 , i/o p1 -i/o p4 data in put / ou tput i/o synchronous v dd , v ddq core p ower, i/o p ower supply n/a v ss ground supply n/a 128k x 36, 256k x 18 3.3v synchronous srams 3.3v i/o, pipelined outputs burst counter, single cycle deselect as8c403600 AS8C401800
6.42 2 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk. symbol pin function i/o active description a 0 -a 17 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of c lk and adsc lo w o r adsp low and ce lo w. adsc address status (cache controller) ilow synchronous address status from cache controller. adsc i s a n active low i nput th at i s use d to l o ad the address registers with new addresses. adsp address status (processor) ilow synchronous address status from processor. adsp i s a n ac tive lo w i nput that is us ed to l oad the address registers with new addresses. adsp is gated by ce . adv burst address advance ilow synchronous address advance. adv i s a n a ctive l ow i nput th at i s u se d to a d vance th e i nternal burst c ounter, controlling b urst access after the initial ad dress is lo aded. when the i nput is high the b urst c ounte r i s n ot i ncremented ; th at i s, th ere i s n o a dd ress a dvance. bwe byte wr ite enable i low synchronous byte write enable gates the byte write inputs bw 1 - bw 4 . if bwe is low at the rising edge of clk then bw x i nputs a re p asse d to th e n e xt s tag e i n the c ircuit. if bwe is high then the byte write inputs are blocked and only gw c an i nitiate a w rite cycle. bw 1 - bw 4 individual byte write e nables ilow synchronous byte write enables. bw 1 controls i/o 0-7 , i/o p1 , bw 2 controls i/o 8-15 , i/o p2 , etc. any active byte write causes all outputs to be disabled. ce chip e nable i low synchronous c hip e nable. ce is used with cs 0 and cs 1 to e nable the as8c403600/1800 . ce al so g ates adsp . clk clock i n/a this i s the clo ck i nput. a ll ti ming r e fe rence s fo r th e d e vice a re made with r espe ct t o th is i nput. cs 0 chip se lect 0 i high synchronous active high c hip select. cs 0 is used with ce and cs 1 to e nable th e c hip . cs 1 chip se lect 1 i low synchronous active low chip select. cs 1 is used with ce and cs 0 to e nable th e c hip. gw global write enable ilow synchronous global write enable. this input will write all four 9-bit data bytes when low on the rising edge of clk. gw supersedes individual byte write enables. i/o 0 -i/o 31 i/o p1 -i/o p4 data in p ut/output i/o n/a synchro nous d ata i np ut/output ( i/o) p ins. b oth th e d ata i nput p ath a nd d ata o utput p ath are reg istere d and triggered by the rising edge of clk. lbo linear b urst o rder i low asynchronous b urst order s election input. when lbo is high, the interleaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo i s a s tatic i nput and m ust not change state while the device is operating. oe output e nable i low asynchronous o utput e nable. when oe is low the data output drivers are enabled on the i/o pins if the chip is also se lected. when oe i s high the i/o p ins are in a hig h-impedance state. tms te st m o de se lect i n/a gives input command for tap controller. sampled on rising edge of tdk. this pin has an internal pullup. tdi te st d ata in p ut i n/a serial input of registers placed between tdi and tdo. sampled on rising edge of tck. this pin has an internal p ullup. tck te s t c lo ck i n/a clock input of tap controller. each tap event is clocked. test inputs are captured on rising edge of tck, while test outputs are driven from the falling edge of tck. this pin has an internal pullup. tdo test da taoutput o n/a serial output of registers placed between tdi and tdo. this output is active depending on the state of the tap controller. zz sleep mode i high asynchronous sleep mode input. zz high will g ate the clk internally and p ower d own the as8c403600/1800 to its lo west p ower consumption le vel. data retention is g uaranteed i n sl eep mode.this p in has an internal p ull d own. v dd po we r s upp ly n/a n/a 3.3v c ore p o we r s upp ly. v ddq power sup ply n/a n/a 3.3v i/o s upply. v ss ground n/a n/a ground. nc no c onne ct n/a n/a nc p ins a re n o t e lectrically c o nnected to th e d evice . 5279 tbl 02
6.42 as8 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range 3 functional block diagram a 0- a 16/17 address register clr a1* a0* 17/18 2 17/18 a 2 ?a 17 128k x 36/ 256k x 18- bit memory array internal address a 0 ,a 1 bw 4 bw 3 bw 2 bw 1 byte 1 write register 36/18 36/18 adsp adv clk adsc cs 0 cs 1 byte 1 write driver byte 2 write driver byte 3 write driver byte 4 write driver byte 2 write register byte 3 write register byte 4 write register 9 9 9 9 gw ce bwe lbo i/o 0 ? i/o 31 i/o p1 ?i/o p4 oe data input register 36/18 output buffer output register d q dq enable register enable delay register oe burst sequence cen clk en clk en q1 q0 2 burst logic binary counter 5279 drw 01 zz powerdown , jtag (sa version) tms tdi tck trst (optional) tdo
6.42 4 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range 100 pin t qfp ca pacitance (t a = +25c, f = 1.0 mhz) recommended operating temperature and suppl y voltage absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supplies have ramped up. power supply sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. t a is the "instant on" case temperature. recommended dc operating conditions notes: 1. v ih (max) = v ddq + 1.0v for pulse width less than t cyc/2 , once per cycle. 2. v il (min) = -1.0v for pulse width less than t cyc/2 , once per cycle. symbol rating commercial & industrial unit v term (2) terminal voltage with respect to g nd -0.5 to +4.6 v v term (3,6) terminal voltage with respect to g nd -0.5 to v dd v v term (4,6) terminal voltage with respect to g nd -0.5 to v dd +0.5 v v term (5,6) terminal voltage with respect to g nd -0.5 to v ddq +0.5 v t a (7) commercial operating temperature -0 to + 70 o c industrial operating temperature -40 to + 85 o c t bias temperature under bias -55 t o + 125 o c t stg storage temperature -55 t o + 125 o c p t power dissipation 2.0 w i out dc output current 50 ma 5279 tbl 03 grade temperature (1) v ss v dd v ddq commercial 0c to + 70c 0v 3.3v5% 3.3v5% industrial -40c to +85c 0v 3.3v5% 3.3v5% 5 279 t bl 04 symbol parameter min. typ. max. unit v dd core s upply voltage 3.135 3.3 3.465 v v ddq i/o supp ly voltage 3.135 3.3 3.465 v v ss supply voltage 0 0 0 v v ih input high voltage - inputs 2.0 ___ _ v dd +0.3 v v ih input high voltage - i/o 2.0 ___ _ v ddq +0.3 (1 ) v v il input low voltage -0.3 (2) ___ _ 0.8 v 5279 t bl 06 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o cap acitance v out = 3dv 7 pf 5279 t bl 07 notes: 1. t a is the "instant on" case temperature. note: 1. this parameter is guaranteed by device characterization, but not production tested.
6.42 idt71v3576, idt71v3578, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial and industrial temperat ure ranges 5 pin configuration C 128k x 36 tqfp top view notes: 1. pin 14 can either be directly connected to v dd , or connected to an input voltage v ih , or left unconnected. 2. pin 64 can be left unconnected and the device will always remain in active mode. 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 b w 4 b w 3 b w 2 b w 1 c s 1 v d d v s s c l k g w b w e o e a d s c a d s p a d v a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c n c n c n c l b o a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 5279 drw 02 v dd /nc (1) i/o 15 i/o p3 nc i/o p4 a 1 5 a 1 6 i/o p1 nc i/o p2 zz (2) ,
6.42 6 idt71v3576, idt71v3578, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial and industrial temperat ure ranges pin configuration C 256k x 18 10099989796959493929190 87868584838281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 n c n c b w 2 b w 1 c s 1 v d d v s s c l k g w b w e o e a d s c a d s p a d v a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c n c n c n c l b o a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 nc nc v ddq v ss nc i/o p2 i/o 15 i/o 14 v ss v ddq i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 v ddq v ss i/o 9 i/o 8 nc nc v ss v ddq nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc v ddq v ss nc i/o p1 i/o 7 i/o 6 v ss v ddq i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 v ddq v ss i/o 1 i/o 0 nc nc v ss v ddq nc nc 5279 drw 03 v dd /nc (1) nc nc nc nc a 1 6 a 1 7 nc nc a 10 zz (2) , tqfp top view notes: 1. pin 14 can either be directly connected to v dd , or connected to an input voltage v ih , or left unconnected. 2. pin 64 can be left unconnected and the device will always remain in active mode.
6.42 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range 7 dc electrical characteristics over the operating temperature and supply voltage range (1) dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 5%) figure 2. lumped capacitive load, typical derating figure 1. ac test load ac test load ac test conditions (v ddq = 3.3v) note: 1. the lbo, tms, tdi, tck and trst pins will be internally pulled to v dd and the zz pin will be internally pulled to v ss if they are not actively driven in the application. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/ tcyc while adsc = low; f=0 means no input lines are changing. 3. for i/os v hd = v ddq - 0.2v, v ld = 0.2v. for other inputs v hd = v dd - 0.2v, v ld = 0.2v. v ddq /2 50 i/o z 0 =50 5279 drw 06 , 1 2 3 4 20 30 50 100 200 tcd (typical, ns) capacitance (pf) 80 5 6 5279 drw 07 , symbol parameter test conditions min. max. unit |i li | input le akage current v dd = max., v in = 0v to v dd ___ 5a |i lzz | zz, lbo and j tag input le akage current (1 ) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current v out = 0v to v ddq , device deselected ___ 5a v ol output low voltage i ol = +8ma, v dd = min. ___ 0.4 v v oh output h igh voltage i oh = -8ma, v dd = min. 2.4 ___ v 5279 t bl 0 8 symbol parameter test conditions 150mhz 133mhz unit com'l ind com'l ind i dd operating power supply current device selected, outputs open, v dd = m ax., v ddq = m ax., v in > v ih or < v il , f = f max (2) 295 305 250 260 ma i sb1 cmos standby po wer supply current device deselected, outputs open, v dd = m ax., v ddq = m ax., v in > v hd or < v ld , f = 0 (2,3) 30 35 30 35 ma i sb2 clock run ning power supply current device deselected, outputs open, v dd = m ax., v ddq = m ax., v in > v hd or < v ld , f = f max (2,3) 105 115 100 110 ma i zz full sleep mode supply current zz > v hd, v dd = m ax. 30 35 30 35 ma 5279 t bl 0 9 inp ut p ulse le ve ls inp ut r ise /fall t ime s inp ut t iming re fe re nce l e ve ls output timing reference le vels ac test load 0 to 3v 2ns 1.5v 1.5v see figure 1 5 279 t bl 10
6.42 8 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range synchronous truth table (1,3) notes: 1. l = v il , h = v ih , x = dont care. 2. oe is an asynchronous input. 3. zz = low for this table. operation address used ce cs 0 cs 1 adsp adsc adv gw bwe bw x oe (2) clk i/o deselected cycle, p ower d own nonehxx x l xxxxx -hi-z deselected cycle, p ower d own nonelxh l x xxxxx -hi-z deselected cycle, p ower d own nonellx l x xxxxx -hi-z deselected cycle, p ower d own nonelxhx l xxxxx -hi-z deselected cycle, p ower d own nonellx x l xxxxx -hi-z read cy cle, b egin b urst external l h l l x x x x x l - d out read cy cle, b egin b urst external l h l l x x x x x h - hi-z read cy cle, b egin b urst external l h l h l x h h x l - d out read cy cle, b egin b urst external l h l h l x h l h l - d out read cy cle, b egin b urst external l h l h l x h l h h - hi-z write cycle, begin burst external l h l h l x h l l x - d in write cycle, begin burst external l h l h l x l x x x - d in read c ycle, continue b urst next x x x h h l h h x l - d out read c ycle, continue b urst next x x x h h l h h x h - hi-z read c ycle, continue b urst next x x x h h l h x h l - d out read c ycle, continue b urst next x x x h h l h x h h - hi-z read c ycle, continue b urst next h x x x h l h h x l - d out read c ycle, continue b urst next h x x x h l h h x h - hi-z read c ycle, continue b urst next h x x x h l h x h l - d out read c ycle, continue b urst next h x x x h l h x h h - hi-z write cycle, continue b urst next x x x h h l h l l x - d in write cycle, continue b urst next x x x h h l l x x x - d in write cycle, continue b urst next h x x x h l h l l x - d in write cycle, continue b urst next h x x x h l l x x x - d in read c ycle, s uspend b urst current x x x h h h h h x l - d out read c ycle, s uspend b urst current x x x h h h h h x h - hi-z read c ycle, s uspend b urst current x x x h h h h x h l - d out read c ycle, s uspend b urst current x x x h h h h x h h - hi-z read c ycle, s uspend b urst current h x x x h h h h x l - d out read c ycle, s uspend b urst current h x x x h h h h x h - hi-z read c ycle, s uspend b urst current h x x x h h h x h l - d out read c ycle, s uspend b urst current h x x x h h h x h h - hi-z write cycle, suspend burst current x x x h h h h l l x - d in write c ycle, s uspend b urst currentxxx h hhlxxx -d in write cycle, suspend burst current h x x x h h h l l x - d in write cycle, suspend burst current h x x x h h l x x x - d in 5279 tbl 11
6.42 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range 9 linear burst sequence t able ( lbo =v ss ) synchronous write function truth table (1, 2) asynchronous truth table (1) interleaved burst sequence table ( lbo =v dd ) notes: 1. l = v il , h = v ih , x = dont care. 2. bw 3 and bw 4 are not applicable for the AS8C401800. 3. multiple bytes may be selected during the same cycle. notes: 1. l = v il , h = v ih , x = dont care. 2. synchronous function pins must be biased appropriately to satisfy operation requirements. note: 1. upon completion of the burst sequence the counter wraps around to its initial state. note: 1. upon completion of the burst sequence the counter wraps around to its initial state. operation gw bwe bw 1 bw 2 bw 3 bw 4 r e a d hhxxxx r e a d hl hhhh write all b ytes l x x x x x write all b ytes h l l l l l write b yte 1 (3 ) hl l hhh write b yte 2 (3 ) hl hlhh write b yte 3 (3 ) hl hhl h write b yte 4 (3 ) hl hhhl 5279 tbl 12 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11000110 5279 tbl 15 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11100100 5279 tbl 14 operation (2) oe zz i/o status power read l l data o ut active read h l high-z active write x l high-z C data in active deselected x l high-z standby sleep mode x h high-z sleep 5279 tbl 13
6.42 10 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range ac electrical characteristics (v dd = 3.3v 5%, commercial and industrial temperature ranges) notes: 1. measured as high above v ih and low below v il . 2. transition is measured 200mv from steady-state. 3. device must be deselected when powered-up from sleep mode. 4. t cfg is the minimum time required to configure the device based on the lbo input. lbo is a static input and must not change during normal operation. 150mhz 133mhz symbol parameter min. max. min. max. unit t cy c clock cycle time 6.7 ____ 7.5 ____ ns t ch (1 ) clock hi gh p ulse w idth 2.6 ____ 3 ____ ns t cl (1) clock low pulse width 2.6 ____ 3 ____ ns output parameters t cd clo ck high to v alid data ____ 3.8 ____ 4.2 ns t cd c clock hi gh to data cha nge 1.5 ____ 1.5 ____ ns t cl z (2) clock hi gh to o utput active 0 ____ 0 ____ ns t chz (2 ) cloc k high to data hi gh-z 1.5 3.8 1.5 4.2 ns t oe output e nable a ccess time ____ 3.8 ____ 4.2 ns t ol z (2 ) output enable lo w to output active 0 ____ 0 ____ ns t ohz (2) output enable high to o utput high-z ____ 3.8 ____ 4.2 ns set up times t sa address setup time 1.5 ____ 1.5 ____ ns t ss address status setup time 1.5 ____ 1.5 ____ ns t sd data in s etup time 1.5 ____ 1.5 ____ ns t sw write setup time 1.5 ____ 1.5 ____ ns t sav address advance setup time 1.5 ____ 1.5 ____ ns t sc chip enable/select setup time 1.5 ____ 1.5 ____ ns hold times t ha address hold time 0.5 ____ 0.5 ____ ns t hs address s tatus hold time 0.5 ____ 0.5 ____ ns t hd data in ho ld time 0.5 ____ 0.5 ____ ns t hw write hold time 0.5 ____ 0.5 ____ ns t hav address advance hold time 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ ns sleep m ode and configuration p arameters t zzp w zz pulse width 100 ____ 100 ____ ns t zzr (3) zz r e co ve ry t ime 100 ____ 100 ____ ns t cfg (4 ) configuration s et-up time 27 ____ 30 ____ ns 52 79 t bl 16
6.42 idt71v3576, idt71v3578, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial and industrial temperat ure ranges 11 notes: 1. o1 (ax) represents the first output from the external address ax. o1 (ay) represents the first output from the external address ay; o2 (ay) represents the next output data in the burst sequence of the base address ay, etc. where a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. zz input is low and lbo is don't care for this cycle. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. timing waveform of pipelined read cycle (1,2) t c h z t s a t s c t h s g w , b w e , b w x t s w t c l t s a v t h w t h a v c l k a d s c ( 1 ) a d d r e s s t c y c t c h t h a t h c t o e t o h z o e t c d t o l z o 1 ( a x ) d a t a o u t t c d c o 1 ( a y ) o 3 ( a y ) o 2 ( a y ) o 2 ( a y ) t c l z a d v c e , c s 1 ( n o t e 3 ) p ip e lin e d r e a d b u r s t p ip e lin e d r e a d o u t p u t d is a b le d a x a y t s s o 1 ( a y ) ( b u r s t w r a p s a r o u n d to its in itia l s ta te ) o 4 ( a y ) 5 2 7 9 d r w 0 8 a d s p a d v h i g h s u s p e n d s b u r s t ,
6.42 12 idt71v3576, idt71v3578, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial and industrial temperat ure ranges notes: 1. device is selected through entire cycle; ce and cs 1 are low, cs 0 is high. 2. zz input is low and lbo is don't care for this cycle. 3. o1 (ax) represents the first output from the external address ax. i1 (ay) represents the first input from the external address ay; o1 (az) represents the first output from the external address az; o2 (az) represents the next output data in the burst sequence of the base address az, etc. where a0 and a1 are advancing for the four word burst i n the sequence defined by the state of the lbo input. timing waveform of combined pipelined read and write cycles (1,2,3) c l k a d s p a d d r e s s g w a d v o e d a t a o u t t c y c t c h t c l t h a t s w t h w t c l z a x a y a z t h s i1 ( a y ) t s d t h d t o l z t c d t c d c d a t a i n ( 2 ) t o e o 1 ( a z ) o 1 ( a z ) s in g le r e a d p ip e lin e d b u r s t r e a d p ip e lin e d w r it e o 1 ( a x ) t o h z t s s t s a o 3 ( a z ) o 2 ( a z ) 5 2 7 9 d r w 0 9 t c d ,
6.42 idt71v3576, idt71v3578, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial and industrial temperat ure ranges 13 notes: 1. zz input is low, bwe is high and lbo is don't care for this cycle. 2. o4 (aw) represents the final output data in the burst sequence of the base address aw. i1 (ax) represents the first input from the external address ax. i1 (ay) represents the first input from the external address ay; i2 (ay) represents the next input data in the burst sequence of the base address ay, etc. where a0 and a1 are advan cing for the four word burst in the sequence defined by the state of the lbo input. in the case of input i2 (ay) this data is valid for two cycles because adv is high and has suspended the burst. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. timing waveform of write cycle no. 1 - gw controlled (1,2,3) a d d r e s s c l k a d s p a d s c t c y c t s s t h s t c h t c l t h a t s a a x a y a z a d v d a t a o u t o e t h c t s d i 1 ( a x ) i 1 ( a z ) i 2 ( a y ) t h d t o h z d a t a i n t h a v o 3 ( a w ) o 4 ( a w ) c e , c s 1 t h w g w t s w ( n o t e 3 ) i 2 ( a z ) b u r s t w r it e b u r s t r e a d b u r s t w r ite s in g le w r it e i 3 ( a z ) i 4 ( a y ) i 3 ( a y ) i 2 ( a y ) t s a v ( a d v h i g h s u s p e n d s b u r s t ) i 1 ( a y ) g w is ig n o r e d w h e n a d s p in it ia t e s a c y c le a n d is s a m p le d o n t h e n e x t c lo c k r is in g e d g e t s c 5 2 7 9 d r w 1 0 ,
6.42 14 idt71v3576, idt71v3578, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial and industrial temperat ure ranges timing waveform of write cycle no. 2 - byte controlled (1,2,3) a d d r e s s c l k a d s p a d s c t c y c t s s t h s t c h t c l t h a t s a a x a y t h w b w x a d v d a t a o u t o e t h c t s d s in g le w r ite b u r s t w r it e i 1 ( a x ) i 2 ( a y ) i 2 ( a y ) ( a d v s u s p e n d s b u r s t ) i 2 ( a z ) th d b u r s t r e a d e x t e n d e d b u r s t w r it e t o h z d a t a i n t s a v t s w o 4 ( a w ) c e , c s 1 t h w b w e t s w ( n o t e 3 ) i 1 ( a z ) a z i4 ( a y ) i1 ( a y ) i4 ( a y ) i 3 ( a y ) t s c b w e is ig n o r e d w h e n a d s p in it ia t e s a c y c le a n d is s a m p le d o n n e x t c lo c k r is in g e d g e b w x is ig n o r e d w h e n a d s p in it ia t e s a c y c le a n d is s a m p le d o n n e x t c lo c k r is in g e d g e i 3 ( a z ) o 3 ( a w ) 5 2 7 9 d r w 1 1 , notes: 1. zz input is low, gw is high and lbo is don't care for this cycle. 2. o4 (aw) represents the final output data in the burst sequence of the base address aw. i1 (ax) represents the first input from the external address ax. i1 (ay) represents the first input from the external address ay; i2 (ay) represents the next input data in the burst sequence of the base address ay, etc. where a0 and a1 are advan cing for the four word burst in the sequence defined by the state of the lbo input. in the case of input i2 (ay) this data is valid for two cycles because adv is high and has suspended the burst. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high.
6.42 idt71v3576, idt71v3578, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial and industrial temperat ure ranges 15 timing waveform of sleep (zz) and power-down modes (1,2,3) t c y c t s s t c l t c h t h a t s a t s c t h c t o e t o l z t h s c l k a d s p a d s c a d d r e s s g w c e , c s 1 a d v d a t a o u t o e z z s in g le r e a d s n o o z e m o d e t z z p w 5 2 7 9 d r w 1 2 o 1 ( a x ) a x ( n o te 4 ) t z z r a z , notes: 1. device must power up in deselected mode 2. lbo is don't care for this cycle. 3. it is not necessary to retain the state of the input registers throughout the power-down cycle. 4. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs1 are low on this waveform, cs 0 is high.
6.42 16 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range clk adsp gw,bwe,bwx ce, cs 1 cs 0 address adsc data out oe av aw ax ay az (av) (aw) (ax) (ay) 5279 drw 14 , non-burst read cycle timing waveform notes: 1. zz input is low, adv is high and lbo is don't care for this cycle. 2. (ax) represents the data for address ax, etc. 3. for read cycles, adsp and adsc function identically and are therefore interchangable. notes: 1. zz input is low, adv and oe are high, and lbo is don't care for this cycle. 2. (ax) represents the data for address ax, etc. 3. although only gw writes are shown, the functionality of bwe and bw x together is the same as gw . 4. for write cycles, adsp and adsc have different limitations. non-burst write cy cle timing w a veform clk adsp gw ce, cs 1 cs 0 address adsc data in av aw ax az ay (av) (aw) (ax) (az) (ay) 5279 drw 15 ,
6.42 as8c403600, AS8C401800, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, pipelined outputs, burst counter, single cycle deselect commercial temperature range 17 p acka as6c 8016 -55 x x n device number package option temperature range 80 = 8m z - 44pin tsop i = industrial low power sram prefix 16 = x16 access time b = 48ball tfbga (-40 to + 85 c) n = lead free rohs compliant part alliance organ iza tion vcc range package operating temp speed mhz as8c403600-qc150n 128k x 36 3.1 - 3.4v 100 pin tqfp commercial: 0 c - 70c 150 AS8C401800-qc150n 256k x 18 3.1 - 3.4v 100 pin tqfp commercial: 0 c - 70c 150 part numbering system ? alliance memory, inc. 551 taylor way, suite#1, san carlos , ca 94 070 tel: 6 50- 610 -6800 fax: 650- 620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved part number: as 8c403600/401800 document version: v. 1.0 ? copyright 2003 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or re gistered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are pos sible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or customer. alliance do es not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warra nties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, e xcept as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from allia nce does not convey a license under any patent rights, copyrig hts; mask works rights, trademarks, or any other intellectual property rights of allianc e or third parties. alliance do es not authorize its products fo r use as critical components in life-supporting systems where a malfunction or failure may reasonabl y be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to inde mnify alliance against all claims arising from such use. ordering information ordering information alliance organ iza tion vcc range package operating temp speed ns as6c8016a -55zin 512k x 16 2.7 - 5.5v 44pin tsop ii industrial ~ -40 c - 85 c 55 as6c8016a -55bin 512k x 16 2.7 - 5.5v 48ball fb ga industrial ~ -40 c - 85 c 55 part numbering system as6c 8016 -55 x x n device number package option temperature range 80 = 8m z - 44pin tsop i = industrial low power sram prefix 16 = x16 access time b = 48ball tfbga (-40 to + 85 c) n = lead free rohs compliant part as8c 01= zbt q = 100 pin tqfp sync. sram prefix 18= x18 36 = x36 25 = flow- thru 0 ~ 70c 150mhz n= leadfree 0 = m 00 = pipelined speed device conf. mode package operati ng temp n

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